As integrated circuits (“IC”) have grown in complexity, the development and testing of the circuits has become increasingly difficult and demanding. Modern IC's may comprise transistors and the like that number into the millions, with a multiple of that number of transistor connection paths. In IC's, a signal must propagate through a number of gates and latches until it reaches its final destination. Gates may be thought of as simple logic switches that are either open or closed. Latches generally are comprised of one or more gates, and are capable of storing or “holding” an input signal until a desired event occurs, such as a clock tick, when the “held” signal is released. For example, a latch may receive an input first signal and “hold” it until a second input arrives at which time the latch transmits the “held” first signal.
As it propagates through the IC, a signal will encounter various delays, generally in the form of “gate delay” and “wire delay”. Gate delay refers to time required for transistors such as “and gates,” “or gates,” “nor gates,” etc. to operate. Wire delay refers to delay caused by the resistance of the carrying medium and other resistors, capacitors, and the like that are encountered between gates. In sum, the gate delay and wire delay that occurs along a connection path between latches may be referred to as the “path delay” between those latches.
Excessive delays can be disastrous to an IC. The IC may not be able to perform a desired application if it responds too slowly as latches operate out of sequence. Also, less than predicted delay raises the possibility of a so-called race condition that arises when one signal arrives at a desired destination out of sequence with another signal. Proper sequencing and stacking are critical to IC performance.
Circuits are generally provided with a clock signal for controlling the sequence of circuit operations. The clock signal in IC's generally comprises a continuous square wave signal that alternates between a high and a low voltage level. The clock signal can be used to control the sequence of IC logic by, for example, new data being presented to the inputs of various circuits every time the clock signal goes from high to low. It is critical for an IC manufacturer to provide IC's that meet their specified clock speed.
Various systems and methods are known for determining IC clock speeds and for insuring that the chip operates in the correct timing sequence. For modem day complex IC's, these systems and methods typically take the form of software circuit modeling tools. These timing tools generally operate by determining the path delay between latches as the signal propagates through the IC to determine a total delay.
As circuits have become increasingly larger and more complex, problems with these software timing modeling systems and methods have become apparent. Many of these problems relate to the resources required to use the systems. For example, running a timing model to test a very large system integration (VLSI) IC with its millions of paths and latches can require enormous amounts of memory and consume inordinate processor time. Often, memory and processing requirements are so large as to require dedicated and expensive memory systems. Also, required memory can become so great during the run that the available resources are exceeded and the test program crashes.
Solutions to these problems have been proposed. For example, the complexity of a timing analysis can be reduced by modeling an IC as a collection of connected sub-circuits. So-called “black box” timing models analyze these sub-circuits individually to determine purely “internal” sub-circuit delay. A total delay is assigned to each sub-circuit. To analyze the timing of the overall IC, or the “global” timing, these black box methods then consider the delay on the paths connecting the individual sub-circuits to one another, or “global paths,” with no consideration given to internal operation of the sub-circuits other than use of the previously determined total delay.
While these simple black box models can reduce the memory requirements for running global timing tests, they have been discovered to be disadvantageous for some purposes. For example, by eliminating consideration of sub-circuit internal timing, these models are unable to model transparency effects.
Modeling transparency effects generally considers timing through transparent latches. Latches may be edge-triggered or level-triggered. Edge triggered devices generally sample a signal only upon the detection of the leading edge of a clock high or low signal. Edge triggered latches are generally referred to as being subject to fixed timing, with the time at which a signal is communicated being known and equal to the detection of the edge of the clock high signal. Level triggered latches, on the other hand, may be referred to as being transparent for timing purposes. Level triggered latches are activated and in an “on” state the entire time that the clock signal is in either its high (or low) state. Signals will be communicated any time they are received and the latch is in the on state. Level triggered latches thereby may be described as having a timing “window” to receive signals, with the window starting at the beginning of the clock high (or low) level signal and ending at the end of the high (or low) level signal.
In addition to black box models, an additional proposed solution to problems associated with required resources for timing models is to use so called “pruning” techniques to reduce the complexity of IC's. With these methods, a latch having a plurality of paths leading into it will have all but the path having the largest delay removed from consideration, or “pruned.” The timing model will then be run with consideration of only that largest delay. Generally, the underlying assumption of such pruning practices is that global timing will only be affected by the worst-case path having the largest delay. By way of example, assume three global paths connect three different latches from three different blocks with a single latch in a fourth block. Pruning would remove all but the path having the largest delay from consideration.
Although pruning reduces the complexity of IC's for modeling, the practice as presently known is not without problems. For example, secondary global paths that have been pruned, although not being worst case, may yet have such a large delay associated with them that they are “broken.” That is, the delay with a pruned path may be large enough that it will prevent the circuit from achieving its required speed. When the path is pruned, however, it is removed from the model and its broken status will not be detected.
Still an additional proposed solution comprises so-called “gray box” models. A gray box model may be thought of as a black box model with additional block detail. In particular, gray box models generally comprise block models having summed path delays for each path in the block. While these models may contain sufficient detail to perform global timing modeling, the level of detail they contain has proven to require substantial memory and processing resources. For substantial circuits such as VLSI IC's, in fact, gray box models have presented problems related to excessive memory and processing resource requirements.
These and other problems in the art remain heretofore unresolved.